Microprocessors

yottabyte

Memory called RDRAM that conforms to the RIMM form factor.

CISC

Two.

The LGA 775, or Socket T, is an Intel CPU socket for the desktop. Its job is to provide mechanical and electrical connections between the microprocessor and the PCB. LGA stands for Land Grid Array.

On-chip memory is a memory that resides on microcontroller itself. e.g RAM.

It may be one of the Internal RAM or Special Function Register (SFR).

Off-chip memory is external ROM or EPROM.

MP IS cpu it self

1) it is 16 bit mp

2) it is fabricated using HMOS TECHOLOGY.

3) IT CONTAIN approximately 29000 transistor.

4) 8086 is 40 pin dip ic

5)it required +5v power supply

6) itrequired 5 mhz external clock frq .

7) it has

20bit AB

16BIT DB

6BYTE IQ

2 EXTERNAL H/W

256 S/W

hi frenz here is an ALP on fibbonacci series......

source code:

mov si,2000(2000 is a address location of si register)

mov cx,05 (cx is a count register for how many values we have to given)

mov al,00 (initially we have 2 initialize al register at starting point....)

mov [si],al

mov bl,01

inc si

mov [si],bl

add al,bl

mov dl,al

mov al,bl

mov bl,al

inc si

mov [si,dl

dec cx

jnz (address of the location add al,bl jump)

hlt

The purpose of a translation look aside buffer is to improve virtual address translation speed. There is at least one translation look aside buffer in all laptop, desktop, and server processors.

Timer means time between the signal waves

mov H , L mov is opcode H L are operands

to make work faster

Under normal circumstances, you can't erase or add any information to a?

#include <p18f4580.h>

#pragma config OSC = IRCIO67

#pragma config WDT = OFF

#pragma config LVP = OFF

#pragma config PBADEN =OFF

#define Q1 PORTDbits.RD0

#define Q2 PORTDbits.RD3

#define Q3 PORTDbits.RD1

#define Q4 PORTDbits.RD2

#define SW1 PORTBbits.RB1

#define SW2 PORTBbits.RB2

#define SENSOR1 PORTBbits.RB3

#define SENSOR2 PORTBbits.RB0

void main()

{ TRISB = 0;

PORTB = 0;

TRISD = 0;

PORTD = 0;

while (1)

{

if ((SW1==1)&&(SW2==0)&&(SENSOR1==0)&&(SENSOR2==0))

{

Q1=1; //clockwise

Q4=1;

Q2=0;

Q3=0;

}

else if ((SW1==0)&&(SW2==0)&&(SENSOR1==1)&&(SENSOR2==0))

{

Q1=0;

Q2=0;

Q3=0;

Q4=0;

}

else if ((SW1==0)&&(SW2==1)&&(SENSOR1==0)&&(SENSOR2==0))

{

Q2=1; //counter clockwise

Q3=1;

Q1=0;

Q4=0;

}

else if ((SW1==0)&&(SW2==0)&&(SENSOR1==0)&&(SENSOR2==1))

{

Q1=0;

Q2=0;

Q3=0;

Q4=0;

}

}

A CPU processor or central processing unit controls the functions of most electronic products. The CPU accepts the input data, processes the information and sends it to the component that is in charge of executing the action. CPUs are also known as microprocessors and are at the center of any computer system. Although CPUs are most often thought of as a computer chip, they can also be found in many other electronic devices including cell phones, hand held devices, microwaves, television sets and toys.

those which have single operand e.g mov A

Core capabilities are those skills that differentiate the manufacturing from its competitors

TTL

offset storage for forming physical address

Intel Core Duo

Intel Core 2 Duo Intel Core 2 Quad Intel Celeron AMD Athlon XP

AMD Phenom X2

And two for laptops:

Intel Atom

AMD Turion X2

It's impossible :o) You can disable and enable any interrupt source by setting or clearing corresponding bit in proper control register. Show me your code - we will see what can be done wrong.

Asar

fotousa@interia.pl

You can set bit I on SREG by 1 to enable global interrupt or by 0 to disable it.

in c programming you can write

#asm ("sei") //to enable global interupt

#asm ("cli") //to disable global interupt

M. Wicaksono A.

It buffers and routes data from source to another It buffers and routes data from source to another

Cache is a high speed memory which is basically used for the following reason:

As the speed of the main memory is not as much as the speed of the CPU.so just to compensate the speed mistmatch between the CPU and main memory the cache is used in between the two.so whenever the CPU asks for any data its being checked with the cache memory and if present then "cache hit" occurs or else "cache miss" occurs wher the CPU takes the data form the main memory and that data's cpoy is being send to the cache for any further operation where the CPU can request for the same data.

Anand bhat(mca@kiit-870024)

Yes.

Bigger number = better.

Data segment

msg1 db 10,13,'enter the string: $'

msg2 db 10,13,'string is palindrome$'

msg3 db 10,13,'string is not palindrome$'

new db 10,13,'$'

inst db 20 dup(0)

data ends

code segment

assume cs:code,ds:data

start:

mov ax,data

mov ds,ax

lea dx,msg1

mov ah,09h

int 21h

mov bx,00

up:

mov ah,01h

int 21h

cmp al,0dh

je down

mov [inst+bx],al

inc bx

loop up

down:

mov di,0

dec bx

jnz check

check:

mov al,[inst+bx]

cmp al,[inst+di]

jne fail

inc di

dec bx

jnz check

lea dx,new

mov ah,09h

int 21h

lea dx,msg2

mov ah,09h

int 21h

jmp finish

fail:

lea dx,msg3

mov ah,09h

int 21h

finish:

int 3

code ends

end start

end