Intel 8085

8527 DMA controller

The 8527 controller has four independent channels each of which contains an address register and a counter. The counter decrements as each byte transfer occurs, and forces termination of the DMA operation after the last transfer. The controller increments the address register after each operation, so that successive data transfers are made at contiguous ascending addresses.

The arbiter resolves conflicts among the channels for access to memory. Two methods have been used in this chip to make the chip useful in a variety of different applications. In one mode the channels have a fixed priority and conflicts are resolved according to the priority, for example, Channel 0 has highest priority and Channel 3 lowest. The second mode is a rotating priority scheme in which priority rankings are the four cycle shifts of 0-1-2-3, when a channel is granted access to the bus the priority ranking shifts cyclically to place the channel in the lowest priority position for the next arbitration cycle.

Structure of the 8527 DMA controller

The chip has four signals associated with the READ and WRITE operation. MEM READ L and MEM WRITE L are signals produced by DMA controller to exercise memory. The two signals I/O READ L and I/O WRITE L are bidirectional, they are inputs from the microprocessor when the microprocessor sends commands to the 8257 and reads back the 8257 status. During the I/O operation these signals are output from the 8257 and are functionally opposite to the memory signals. The 8257 takes control of the bus by exercising HALT (HRQ) and receives back the "go-ahead" signal on HALT ACKNOWLEDGE (HLDA).

Two signals produced by the DMA controller can be used by the I/O port to assist in controlling the transfer process. One signal TC--terminal count--is asserted during the last cycle of a DMA block. This can be used to describe a DMA mode on an I/O port or to reset the port's internal state to indicate the end of a transfer. The second--MARK--is inserted when the remaining count on a channel became a multiple of 128--providing a convenient timing signal for an external device.

Block Diagram

Pin Configuration

Three Transaction Methods for Peripheral IOs:

• Programmed IOs (like 8255 port used without handshake and Intr signals)

• Interrupt Driven IOs (like 8255 port used without handshake and Inter signals)

• DMA Transactions using a DMAC

Direct Memory Access Control (Peripheral Transactions Server) IOs

· Controller or server sends hold request for processor to grant on acknowledgement, the access to address and data buses, IORD, IOWR, MEMRD, MEMWR and IO buses.

· Once programmed for address of RAM block for transfer and for data counts of IO transactions with RAM, interrupts only at the end of a block transaction or last transaction.

8257 Four Channel DMAC Features:

· Four channels,

· Priority Resolution support,

· TC output and Mark output (after 126 bytes transfer) for interrupts to processor for attention,

· Auto-load on TC mode support for repeat transactions without reprogramming TC and MAR and mode,

· TTL level inputs/outputs compatible with INTEL families.

Well, in the end, for a laptop, with that kind of processing speed, it all comes down to how much computer memory the laptop has. It would be useful to know this beforehand, however, if the RAM is less than 512mb, i would not recommend buying it.

What else it depends on is what operating system it would be running.

Process executes tsl A, lock in order to gain access. If it finds lock 0,

thereby allowing another process to enter. Since TSL is atomic the processes

will take turns executing TSL.

register:- Each flip-flop is a binary cell capable of storing one bit of information. A Register is simply a group of flip-flops. An n-bit register has a group of n flip-flops. The basic function of a register is to hold information within a digital system so as to make it available to the logic elements during the computing process. Since a register consists a finite number of flip-flops and as each of those flip-flops is capable to store a single 0 or 1, there are a finite number of 0-1 combinations that can be stored into a register. Each of those combinations is known as state or content of that register. With flip-flops we can store data bitwise but usually data does not appear as single bits. Instead it is common to store data words of n bit with typical word lengths of 4, 8, 16, 32 or 64 bit. Thus, several flip-flops are combined to form a register to store whole data words. Registers are synchronous circuits thus all flip-flops are controlled by a common clock line. As registers are often use to collect serial data they are also called accumulators.

Counters:- A counter is a sequential circuit that - counts. That means it proceeds through a pre-defined sequence of states where the state of the circuit is determined by the states of all its flip flops. As every state of the circuit can be given a number we can say that a counter produces a sequence of numbers. A commonly used approach is to interpret a circuits state as dual number, so if flip-flop A,B and C are all 0 the counter's state is 0. if A is 1, B is 0 and C is 1 the counter's state is 101 = 5 and so on. The most basic counters will simply increment by 1 with every clock pulse, so after state 100 it will go to 101; the next pulse will let it switch to 110 etc. It is possible to design counters with any needed counting sequence.