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Intel 8085
Introduced by Intel in 1977, the Intel 8085 is an 8-bit microprocessor that is binary-compatible with Intel 8080. It only requires a +5-volt power supply and has been used as a microcontroller.
1,493 Questions
What is the use of direction flag and Trace flag in 8086?
The direction flag (DF) controls the direction of repeated string instructions. The trap flag (TF) executes one instruction and then executes a debug (INT 1) instruction so that a debugger can single step through a program.
Yes, the 1.7 with 2mb L2 cache will work great, but it means a complete disassembly of the laptop in order to get at the cpu socket.
The carry flag bit is not modified by which arithmetic operation in 8086?
increment and decrement operations ie INC and DEC
Why zero flag is not set in INX instruction of microprocessor 8085?
Because that is the way Intel designed the INX instruction of the 8085. The 8080 is also the same. INX increments (and DCX decrements) the 16 bit register pairs or BC, DE or HL, depending on what register pair you specify in the INX (or DCX) instruction. To check is the value is 0 after an INX (or DCX) instruction, you need to OR the values of the register pair into the A register. For example.....
INX H ;increment HL register pair
MOV A,H ; move H register into the accumulator
ORA L ; Logical OR it with the L register
JZ ADDR ; If 0 then jump to ADDR
How do you draw timing diagram for 8085 instruction LHLD 5000H?
There is an example of a LHLD 5000H diagram on this website: atelier-drachenhaus.de/timing-diagram-8085. This will provide an idea of how to draw the diagram.
Address location to Otis Spunkmeyer Austin plant?
The Austin Otis Spunkmeyer plant is located at
6301 E Stassney Ln # 7-100
Austin, TX 78744
(512) 385-8822
What is effective address of stack addressing mode?
When you use a stack type instruction, such as PUSH B, you are using the effective address contained in the SP (Stack Pointer) register. In this example, m(SP-1) is set to B, m(SP-2) is set to C, and SP is set to SP-2.
The 8085 instruction MOV M,A requires two machine cycles and 7 T states. Cycle one is 3 T states for opcode fetch, plus 1 T state for opcode decode. Cycle two is 3 T state for operand store. These numbers do not include WAIT states. WAIT states are interposed between T2 and T3 of any memory access cycle, and the total number of WAIT states depends on the READY line.
500 MHz clock what does this mean?
Generally when talking about CPUs or Memory, or any chipset used in electronic devices, the clock refers to the speed of the chip. It is measured in frequency and MHz stands for Mega Hertz. 500 MHz would be very slow for a computer while it would be just fine for a cell phone. Most computers today are around 2.5 GHz to 4.0 GHz. It takes 1000 MHz to make 1 GHz.
What are the Data addressing modes of TMS320C54XX processors?
Addressing Modes for TI TMS320C54xModule by: Douglas L. Jones, Swaroop Appadwedula, Matthew Berry, Mark Haun, Dima Moussa, Daniel Sachs. E-mail the authors
Summary: The TI TMS320C54x microprocessor provides a number of ways to specify the location of data to be used in calculations. Immediate addressing, direct addressing, and indirect addressing are the three main types. Knowing the basic addressing modes of a microprocessor is important because they map directly into assembly language syntax and because the need to use a particular addressing mode often dictates which instruction one picks for a given task.
Microprocessors provide a number of ways to specify the location of data to be used in calculations. For example, one of the data values to be used in an add instruction may be encoded as part of that instruction's opcode, the raw machine language produced by the assembler as it parses your assembly language program. This is known as immediate addressing. Alternatively, perhaps the opcode will instead contain a memory address which holds the data (direct addressing). More commonly, the instruction will specify that an auxiliary register holds the memory address which in turn holds the data (indirect addressing). The processor knows which addressing mode is being used by examining special bit fields in the instruction opcode.
Knowing the basic addressing modes of your microprocessor is important because they map directly into assembly language syntax. Many annoying and sometimes hard-to-find bugs are caused by inadvertently using the wrong addressing mode in an instruction. Also, in any assembly language, the need to use a particular addressing mode often dictates which instruction one picks for a given task.
Chapter five, Data Addressing, in the CPU and Peripherals [link] reference contains extended descriptions of most of the addressing modes described below.
Accumulators: src, dstWhenever the abbreviations src or dst are used in the assembly language syntax description for an instruction, it means that only the accumulators A and B may be used for that particular operand. These are seen everywhere, but two classic examples are ld, which always loads data into an accumulator from somewhere else, and sth/stl, which always store data from an accumulator to somewhere else.Examples: ld *AR5,A ; sets A = (contents of memory location pointed to by AR5) sth B,*AR7+ ; sets (contents of memory location pointed to be AR7) = B, ; and then increments AR7 by one
Memory-mapped Registers: MMR, MMRx, MMRyMany of the TMS320C54x registers are memory-mapped, meaning that they occupy real addresses at the low end of data memory space. The most commonly used of these are the auxiliary registers AR0 through AR7. Whenever the abbreviation MMR is used in the assembly language syntax description for an instruction, it means that any memory-mapped register may be used for that particular operand. Only eight instructions use memory-mapped register addressing: ldm, mvdm, mvmd, mvmm, popm, pshm, stlm, and stm. With mvmm, since the instruction accepts two memory-mapped register operands, MMRx and MMRy, only AR0-AR7 and SP may be used.Do not use an asterisk in front of ARx variables here, since this is not indirect addressing.
Examples: mvmm AR3,AR5 ; sets AR5 = AR3 stm #5,AR2 ; sets AR2 = 5 ldm AR0,A ; sets A = AR0
Immediate Addressing: #k3, #k5, K, #k9, #lkImmediate addressing means that the numerical value of the data is itself provided within the assembly instruction. Various TMS320C54x instructions allow immediate data of 3, 5, 8, 9, or 16 bits in length, which are signified in the assembly language syntax descriptions with one of the above symbols. The 16-bit form is the most common and is signified by #lk. 16-bit immediate values always require an extra instruction word and therefore take an extra machine cycle to execute.An immediate data operand is almost always specified in assembler syntax by prepending a pound sign (#) to the data. Depending on the context, the assembler may assume that you meant immediate addressing anyway.
Examples: ld #0,A ; sets A = 0 cmpm AR1,#1 ; sets flag TC = 1 if AR1 == 1; else TC = 0
Labels make this more complicated. Recall that a label in your assembly code is nothing more than shorthand for the memory address where the labeled code or data is stored. So does an instruction like stm coef,AR2 ; sets AR2 = memory address of label coef
mean to store the contents of memory location coef in AR2, or does it mean to store the memory address coef itself in AR2? The second interpretation is correct. Because the stm instruction has only one form, expecting a #lkimmediate operand, the assembler does not care whether the label is prefixed with a pound sign or not. Still, it would have been better for us to include the pound sign in the above example for clarity.
Many instructions have several versions allowing the use of different addressing modes (see ld for a good example of this). With these instructions, including the pound sign is not optional when specifying immediate addressing. The only safe rule, then, is always to prefix the label with a pound sign if you wish to specify the memory address of the label and not the contents of that address.
If you are not sure how a particular instruction has been assembled, you can always examine the .lst file produced by the assembler, and compare the hexadecimal opcodes listed to the left of the assembly instructions with the assembly opcodes given in the assembly language manual (Chapter 4 of the Mnemonic Instruction Set [link] reference).
Direct Addressing: Smem and othersIn the modes called direct addressing by TI, the instruction opcode contains a memory offset (see the "dma" bits on page 5-8 of the CPU and Peripherals [link] reference) seven bits long, which is combined with either the DP (data pointer) or SP (stack pointer) register to obtain a complete 16-bit data-memory address. This divides the data memory into pages of 128 words each.SP is initialized for you in the core file and should not need to be modified. SP-referenced direct addressing is used by the pshd, pshm, popd, and popm instructions for stack manipulation, as well as by all subroutine calls and returns, which save program addresses on the stack.
DP-referenced direct addressing is available wherever you see the Smem abbreviation in an assembly syntax description. The advantage of DP-referenced addressing over the *(lk) form described in the next section is that DP-referenced addressing will not add an extra instruction word (and corresponding extra machine cycle). The disadvantage is that it is limited to 128 words of contiguous memory, and you have to make sure that DP points to the right 128 words. DP may be changed with the ld instruction as needed.
Examples: ld 10,A ; sets A = (contents of memory location DP + 10) add 6,B ; sets B = B + (contents of memory location DP + 6)
NOTE:Make sure you understand that the numbers 10 and 6 above are interpreted as memory addresses, not data values. To get data values, you would need to use a pound sign in front of the numbers. Absolute Addressing: dmad, pmad, *(lk)/SmemThis seems to be TI's term for all the forms of direct addressing which it does not call direct addressing! It is represented in assembly-instruction syntax-definitions using one of the above abbreviations (*(lk) addressing is available when the syntax definition says Smem). dmaddmad (Data Memory ADdress) operands are used by mvxxdata move instructions and represent 16-bit memory addresses in data memory whose contents are used in the instruction.Example: f3ptr .word 0 ; reserve one word of storage; initialize to 0 . . . . mvdm f3ptr,AR4 ; set AR4 = memory address of f3ptr
pmadpmad (Program Memory ADdress) operands are used by the firs, macd, macp, mvdp, and mvpd instructions, as well as all subroutine calls and branching instructions. They represent 16-bit addresses in program memory whose contents are used in the instruction, or jumped to in the case of branch instructions. Other than subroutine calls and branches, the most common use of a pmad is for the firs instruction.Example: firs *AR3+,*AR4+,coefs
NOTE:coefs is a label in the program section of the code, not the data section. *(lk)*(lk) addressing is a syntactic oddity. The asterisk symbol generally means that indirect addressing is being used (see below), but this is actually direct addressing with a 16-bit data memory address encoded in the instruction's last word. The reason for the asterisk is that TI does set the "I" bit in the opcode, usually denoting indirect addressing, and this form can only be used when an Smem is called for in the assembly syntax. Other bits in the low byte of the first instruction word tell the processor that the "*(lk) exception" is to be used, and to fetch the memory address in the next word (see the MOD bits on page 5-10 of the CPU and Peripherals [link] reference). You can easily recognize this addressing mode in .lst files because the low byte of the first instruction word always equals F8h.Examples: hold .word 1 ; reserve one word of storage and initialize to 1 count .word 0 ; reserve one word of storage and initialize to 0 . . . . ld *(count),B ; sets B = 0 (assuming memory was not changed) st T,*(hold) ; sets (storage location at address hold) = T
Indirect Addressing: Smem, Xmem, YmemIndirect addressing on the TMS320C54x always uses the auxiliary registers AR0 through AR7 and comes in two basic flavors. These are easily recognized from the assembly language syntax descriptions as either Smem orXmem/Ymem. SmemIn Smem indirect addressing, only one indirect address is used in the instruction and a number of variations is possible (see the table on page 5-13 of the CPU and Peripherals [link] reference). An asterisk is always used, which signifies indirect addressing. Any of the registers AR0-AR7 may be used, with optional modifications: automatic post-decrement by one, pre- and post-increment by one, post-increment and post-decrement by n (n being stored in AR0), and more, including many options for circular addressing (which automatically implements circular buffers) and bit-reversed addressing (which is useful for FFTs). Xmem/YmemXmem/Ymem indirect addressing is generally used in instructions that need two different indirect addresses, although there are a few instances where an Xmem by itself is specified in order to save bits in the opcode for other options. In Xmem/Ymem indirect addressing, fewer bits are used to encode the option modifiers in the opcode; hence, fewer options are available: post-increment by one, post-decrement by one, and post-increment by AR0with circular addressing.Examples: stl B,*AR6 ; sets (contents of location pointed to by AR6) = low word of B stl B,*AR6+0% ; sets (contents of location pointed to by AR6) = low word of B, ; then increments AR6 with circular addressing mar *+AR3(-6) ; decrements AR3 by 6 (increment by -6)
NOTE:The mar (modify address register) instruction is unusual in the sense that it takes an Smem operand but does nothing with the data pointed to by the ARx register. Its purpose is to perform any of the allowed register modifications discussed above without having to do anything else. This is often handy when you are using an Xmem/Ymem-type instruction but need to do an ARx modification that is only allowed with an Smem-type operand. SummaryThe ld instruction is illustrative of the many possible addressing modes which can be selected with the proper choice of assembly language syntax: ld #0,A ; immediate data: sets A = 0 ld 0,A ; DP-referenced direct: sets A = (contents of the address DP + 0) ld mydata,A ; DP-referenced direct: sets A = (contents of the address ; DP + lower seven bits of mydata) ld #mydata,A ; immediate data: sets A = 16 bit address mydata ld *(mydata),A ; *(lk) direct: sets A = (contents of the 16 bit address mydata) ld B,A ; accumulator: sets A = B ld *AR1+,A ; indirect: sets A = (contents of address pointed to by AR1), ; and afterwards increments AR1 by one ldm AR2,A ; memory-mapped register: sets A = AR2Copied from discussion, as no response has been received from the discussion... There is no branch or jump instruction in the 8085 or 8086/8088 that has a 10 bit address field. Please specify what microprocessor to which you are referring.
When does the overflow flag in 8086 set?
In the 8086/8088, the overflow flag is set when the result of an arithmetic instruction exceeds the bounds of the signed representation of a number. This is not the same as the carry flag, which is used for the unsigned representation. Both flags get set as needed. You decide which one to pay attention to.
Each data transfer is 3 clock cycles. The first cycle emits address and status, and ALE is used to strobe the low order address. Status is S0, S1, and IO/M- The second cycle sets up the transfer, either floating the data bus for a read, or drving the data bus for a write, and then initiating transfer with RD- or WR-. If READY is not true at the sample point (about the middle of the second cycle) an extra cycle is appended after the second cycle, with all lines frozen, until READY goes true. The third cycle wraps up the transfer. The processor samples data one half cycle before the end of RD- for a read, and it holds the data bus valid for one half cycle after WR- for a write. Up to this point, all cycles are similar. What matters is IO/M-. If high, this is an IO read or IO write; if low, this is a memory read or memory write. However, you have to consider S0 and S1. These are advanced status pins, along with IO/M-, that indicate what the processor is doing. They are emitted at ALE. In addition to indicating IO Read, IO Write, Memory Read, and Memory Write, you can decode Opcode Fetch, Interrupt Acknowledge, and Halt.
The number of data lines required in a 16-bit microprocessor is 16, in the internal view, but could be something else, such as 8, in the external view. In the 8086/8088, the processor is 16 bits, and its internal data bus is 16 bits. The 8086 provides 16 bits on the external bus, but the 8088 provides 8 bits, even though they are the same internal processor - the 8088 simply uses two memory cycles to move one word.
The largest number that can be represented on a 16 bit bus depends on the interpretation of that number. An unsigned 16 bit number ranges from 0 to 65535, so 65535 is the largest value when unsigned. A 16 bit two's complement signed number ranges from -32768 to +32767, so +32767 is the largest value when signed.
10 in BCD code is representd as?
The decimal number 10, represented in BCD is 0001 0000.
If, instead, you mean that you have 10 in BCD and want to know what that means, that is equivalent to 0000 0010 and would be 2 in decimal.
What is the difference between INR B and INX B?
INR B increments the B register as an 8-bit value.
INX B increments the BC register as a 16-bit value.
Scaffolding in Army learning for the facilitator/instructor engages and motivates learners to?
Does 8085 microprocessor have serial input output control?
With tricky programming it is possible to do 9600baud serial coms on an 8085 running at 2meg clock. you can detect the start of a serial comunication using
the 7.5 interupt. This is a software uart.
At 9600baud the bits are 104 microseconds long. and the 7.5 interrupt
push takes 55 microseconds so your code starts executing half way thru
the start bit . Your code has to be written very carefully accounting
for machine cycles to read the state of the SID pin every 104 microseconds
till you have read in a byte and stored it. then you reset the interrupt ready to collect the next byte, after the stop bits or if its comming from something else eg. a PC some time in the future.
I've used it to send and recieve 10 byte packets, take about 10milliseconds
Can you give sample 8086 microprocessor programs?
Mov ax,1234
mov bx,2345
add ax,bx
mov @(some memory location ) say 2200,ax
hlt
What is the need for address and data alignment for DMA transfer?
Data alignment pertains to the starting address of some block of memory being a multiple of the basic data size, such as a 16 or 32 bit word, or being related to the block size of an IO device, such as a disc drive with a sector size of 512 bytes. The 8085 microprocessor, itself, does not care about alignment, as it is an 8 bit computer running on an 8 bit bus. (The 8086 microprocessor does care, because misalignment can cause performance penalties or corruption, but this article deals with the 8085, not the 8086.) External devices, however, such as the 8237 DMA Controller, may well impose limitations on the starting address of a block transfer, because of their internal design. Each case is specific, so you need to consult the documentation of your specific device.
What is an example of a device that communicates through data transfer?
For example, personal digital assistants and cellular telephones communicate with desktop computers through data transfer.
Why rstn has 6 t state in 8085 microprocessors?
4 T-states as usual and 2 more are required to perform n*8
its result gives the vector address of interrupt service routine(rstn is an software interrupt)
