Intel 8086 and 8088

The segment register in the 80806/8088 microprocessor contains the base address (divided by 16) of a region of memory. Since the register is 16 bits in size, there are 65,536 possible segment base addresses, ranging from 00000H to FFFF0H, in increments of 00010H.

After address translation at the instruction level, the generated 16 bit offset is added to the selected segment register times 16 to generate a physical address between 00000H and FFFFFH. (If the offset and base go past FFFFFH, they wrap around back to 00000H.) Since the offset is also 16 bits in size, and since the overlap is only 4 bits (times 16), then each 64 kb segment overlaps by 16 bytes.

There are four segment registers; CS, DS, ES, and SS, standing for Code Segment, Data Segment, Extra Segment, and Stack Segment.

CS is used for opcode fetches. DS is used for normal data. ES is used for certain string operations as the destination address. SS is used for stack and frame (BP) data.

The segment registers can be implicitly selected by context, or they can be explicitly selected with a segment prefix opcode.

Direct addressing mode means the operand address is contained in the instruction. In the 8085, an example is LDA 1234H, which loads the accumulator with the contents of memory location 1234H. In the 8086/8088, an example is MOV AL,[1234H], which accomplishes nearly the same thing.

Indirect addressing mode means the operand address is contained in a register. In the 8085, an example is LDAX B, which loads the accumulator with the contents of the memory location specified in register BC. In the 8086/8088, an example is MOV AL,[BX], which accomplishes nearly the same thing.

Pin Description The following describes the function of each pin: A8 - A15 (Output 3 State) Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0 address,3 stated during Hold and Halt modes. AD0 - 7 (Input/Output 3state) Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address) appear on the bus during the first clock cycle of a machine state. It then becomes the data bus during the second and third clock cycles. 3 stated during Hold and Halt modes. ALE (Output) Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the address to get latched into the on chip latch of peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information. ALE can also be used to strobe the status information. ALE is never 3stated. S0, S1 (Output)

IO/M- (Output) IO/M- indicates whether the Read/Write is to memory or l/O (Tristated during Hold and Halt modes) S0, S1, and IO/M- represent Data Bus Status. Encoded status of the bus cycle: S0 S1 IO/M- 0 0 * Halt State (IO/M- Tristated)

0 1 0 Memory Read

0 1 1 I/O Read

1 0 0 Memory Write

1 0 1 I/O Write

1 1 0 Opcode Fetch

1 1 1 Interrupt Acknowledge S1 can be used as an advanced R/W status. If used this way, it should not be sampled until the trailiing edge of ALE. RD- (Output 3state) READ; indicates the selected memory or I/O device is to be read and that the Data Bus is available for the data transfer. Tristated during Hold and Halt modes. The processor samples the data bus about one half clock cycle before the trailing edge of RD-. WR- (Output 3state)WRITE; indicates the data on the Data Bus is to be written into the selected memory or I/O location. Data is set up at the trailing edge of WR. Tristated during Hold and Halt modes. The data bus is held valid for about one half clock cycle beyond the trailing edge of WR-, or until the leading edge of ALE. It is important to realize that any external bus drivers must not be dropped at the trailing edge of WR- because that creates a race condition - Use ALE to drop the drivers if needed. READY (Input) If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If Ready is low, the CPU will wait for Ready to go high before completing the read or write cycle. It is sampled about one half clock cycle after ALE goes false, on the rising edge of CLK. Note that Ready is sampled about one half clock cycle after the trailing edge of ALE, and this is not a lot of time - make sure your address/ready decoders are fast enough to respond. HOLD (Input) HOLD; indicates that another Master is requesting the use of the Address and Data Buses. The CPU, upon receiving the Hold request. will relinquish the use of buses as soon as the completion of the current machine cycle. Internal processing can continue. The processor can regain the buses only after the Hold is removed. When the Hold is acknowledged, the Address, Data, RD-, WR-, and IO/M- lines are 3stated. HLDA (Output) HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the buses one half clock cycle after HLDA goes low. INTR (Input) INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle of the instruction. If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted. INTA (Output) INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD during the Instruction cycle after an INTR is accepted. It can be used to activate the 8259 Interrupt chip or some other interrupt port. RESTART INTERRUPTS; These three inputs have the same timing as INTR except they cause an internal RESTART to be automatically inserted. RST 7.5 Highest Priority (Edge triggered)

RST 6.5 Medium Priority (Level triggered)

RST 5.5 Lowest Priority (Level triggered) The priority of these interrupts is ordered as shown above. These interrupts have a higher priority than the INTR. They can be masked with the SIM instruction. TRAP (Input) (Edge and Level triggered) Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt. RESET IN- (Input) Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flipflops. None of the other flags or registers (except the instruction register) are affected The CPU is held in the reset condition as long as Reset is applied. RESET OUT (Output) Indicates CPlJ is being reset. Can be used as a system RESET. The signal is synchronized to the processor clock. X1, X2 (Input) Crystal or R/C network connections to set the internal clock generator X1 can also be an external clock input instead of a crystal. The input frequency is divided by 2 to give the internal operating frequency. CLK (Output) Clock Output for use as a system clock when a crystal or R/ C network is used as an input to the CPU. The period of CLK is twice the X1, X2 input period. SID (Input) Serial input data line The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed. SOD (output) Serial output data line. The output SOD is set or reset as specified by the SIM instruction. Vcc+5 volt supply. Vss Ground Reference.

The 8086 has a 20 bit address bus and a 16 bit data bus. The low order 16 bits of the address bus share the same 16 pins as the data bus. The low order 16 bits of the address are emitted in the first clock cycle of a memory access cycle. External logic is expected to latch that address. Then the bus becomes a data bus. The high order 4 bits of the address bus are handled separately.

The determination of operand size (8 bit vs 16 bit) is made by BHE and A0. If BHE is high, it is a 16 bit operand at an even address. If BHE is low and A0 is low, it is an 8 bit operand at an even address. If BHE is low and A0 is high, it is an 8 bit operand at an odd address.