Intel 8085

The full form of LDAX is load accumulator from memory pointed by extended register denoted as "rp". It occupies only one byte in memory and the target address is contained in either the BC or DE register pair.

1)address lines to refer to the address of a block

2)data lines for data transfer

3)IC chips 4 processing data

only general perpose use

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The binary of 300 is 100101100 which are 9 bits therefore the first 8 bits from LSB goes to the register and the carry is generated and carry flag is set to 1.

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A bit is a single digit of a binary number.

The Program Counter and Stack Pointer registers are called special purpose registers because they can not be used arbitrarily; they are, well, special. You cannot, for instance, load a new value into the Program Counter and blithely continue, that action would cause an unconditional jump. Also, the Program Counter is automatically incremented by the size of the instruction, so you can not just put something in it and expect its value to persist. Similarly, you cannot load a new value into the Stack Pointer without losing the entire stack context that you are in.

1 Fetch Instruction from Memory 2 Decode Instruction and Fetch Operands 3 Perform ALU Operations 4 Memory Access (for load/store)5 Store ALU result to register file 6Update PC

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The duration of one T-state is one divided by the clock frequency, or two divided by the crystal frequency. This is for the 8085.

Masking in the 8085 is when certain interrupts are disabled, or masked, by instruction execution. TRAP is not maskable. INTR, RST7.5, RST6.5, and RST5.5 are maskable as a group with the EI and DI instructions. RST7.5, RST6.5, and RST5.5 are selectively maskable, even after the EI instruction, by using the RIM and SIM instructions.

No.

You cannot address 1GB memory with the 8085 or the 8086/8088 without some kind of external demultiplexor that is software controlled. The address bus on the 8085 is 16 bits, giving addressibility of 64KB; while the address bus on the 8086/8088 is 20 bits, giving addressibility of 1MB.

To address 1GB, you need a 30 bit address bus.

28 = 256, so an 8 bit encoder would have a resolution of one part in 256, or 0.39%.

The value being pushed (push [value]) is placed on the top of the stack (esp) and the size of the value is added to esp.

The microprocessor uses an opcode fetch cycle for every instruction because it has to know the opcode in order to execute it, and that is located in memory.

instruction register

Two file modes are "text" and "binary". Text is used for human readable data, such as a C source file, or a notepad text file. Binary is used for computer readable data, such as an executable object file.

Two other file modes are "sequential" and "random". Sequential is used when the file is accessed serially, from the beginning to the end, and can be used for both text and binary files. Random is used when the file is accessed non-serially, often jumping around from place to place. An example of random is a database file.

Yes and no. INTR response requires an opcode fetch sequence from the interrupting hardware device, often a CALL instruction, so there is no vector table in memory for it, because you can CALL any location. On the other hand, some implementations provide an RST instruction as the opcode, making it a vectored interrupt.

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There is no parity interrupt on the 8085 or 8086/8088.

If you mean a memory parity interrupt, that is a function of system design, not a function of the particular microprocessor involved. Generally, a memory parity error is fatal, so one would typically place it on a non-maskable interrupt, such as TRAP on the 8085, or INT 2 (NMI) on the 8086/8088. This assumes, of course, that the memory parity error does not just crash the processor.