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Intel 8086 and 8088
The Intel 8086/8088 family of microprocessors is a 16 bit architecture on a 16 bit (8086) or an 8 bit (8088) bus. The 8088 was the processor in the original IBM PC, and has evolved into the most popular processor used today in PC's and servers.
1,056 Questions
Why DCX D instruction have 6 T states in 8085 microprocessor?
3 T states for instruction fetch, 1 T state for decode, 1 T state for register E decrement, 1 T state for possible register D decrement.
How many words can 8 bits and 16 bits processors transmit at a time?
An 8 bit processor can transmit one letter at a time. In the ASCII code, each of the first 127 combinations of bits has a special standard meaning. The last 127 is given a special meaning. So an an 8 bit processor can transmit 256 bits at a time. An A is 65 bits.
A 16 bit processor can transmit two letters at a time. A B is 66 bits. An E is 69 bits. It can transmit a B and an E. By definition that is considered a word. A difference exists between the way computer people use the language and normal people use it.
Actually, a piece of equipment called a bus attached to the processor does the actual transmitting.
What is the function of the PC register in the 8086 CPU?
There is no PC register in the 8086/8088. It is called the IP register by Intel and it stands for the Instruction Pointer. It contains the address of the current/next instruction to be executed.
What factors determine how much physical memory an 80286 can address?
An 80286 has a 24 bit address bus. As such, it can address 224, or 16,777,216, or 16 MB of memory.
What is the addressing mode of the instruction PCHL in 8085 microprocessor?
It is register addressing mode, as it moves the content of HL to PC which is data and not address.
What is the use of the source index in a 8086 processor?
The Source Index (SI) register is used by certain string type instructions to read from memory. Typically, the instruction is "repeated" with a repeat prefix to iterate through memory until some condition is met.
How good is the celeron processor for laptop Is it worth buying of celeron processor with 1.7GHz?
Well, in the end, for a laptop, with that kind of processing speed, it all comes down to how much computer memory the laptop has. It would be useful to know this beforehand, however, if the RAM is less than 512mb, i would not recommend buying it.
What else it depends on is what operating system it would be running.
Is a Physical address your 911 address?
Your physical address is the MAC (Media Access Control) address that is burned into the network interface card (NIC). That address is unique and is used to find devices within a LAN.
in 8086, there is instruction queue of 6 byte.
It is one of the reason behind giving name.
8086 was introducing pipeline architecture.
What is the use of direction flag and Trace flag in 8086?
The direction flag (DF) controls the direction of repeated string instructions. The trap flag (TF) executes one instruction and then executes a debug (INT 1) instruction so that a debugger can single step through a program.
The carry flag bit is not modified by which arithmetic operation in 8086?
increment and decrement operations ie INC and DEC
What do you mean single and double handshaking of microprocessor 8086?
They are the ways of transmitting parallel data to the microprocessor.
In single handshake, a peripheral device first sends a "Strobe signal" to the microprocessor to indicate that it is ready to send data. The microprocessor , upon detecting the strobe signal, opens up its input port and receives the data. After receiving data, it sends an "Acknowledge signal" to the peripheral to indicate that transmission has been completed.A transmission session has been completed.
In double handshake, first the peripheral device sends a strobe signal, the microprocessor, sends the acknowledge signal to indicate that it is ready to receive data. After which data is received.After sending data, the peripheral sends a strobe signal to indicate data transmission completion, due to which, the microprocessor drops its acknowledge signal and a session has been completed.
The only difference in the two is that, in double handshake, the peripheral is informed about the microprocessor's readiness to receive data. This is doesn't happen in single handshake. So the name follows "double handshake", literally meaning "double confirmation".
Address location to Otis Spunkmeyer Austin plant?
The Austin Otis Spunkmeyer plant is located at
6301 E Stassney Ln # 7-100
Austin, TX 78744
(512) 385-8822
What is multiple processor organization?
A multiprocessor organization for supporting relational data base management systems is presented. DIRECT has a MIMD (multiple instruction stream, multiple data stream) architecture. It can simultaneously support both intra-query and inter-query concurrency. The number of processors assigned to a query is dynamically determined by the priority of the query and the size of the relations it references. The size of a relation is not limited to that of the associative memory as in some previous data base machines. Concurrent updates are controlled through address translation tables which are maintained by a controlling processor. DIRECT is being implemented using LSI-11/03 microprocessors and CCD memories which are searched in an associative manner. A novel cross-point switch is used to connect the LSI-11 processors to the CCD memories. While cross-point switches have proven too expensive for use in general purpose parallel processors, their application in DIRECT demonstrates that these switches can be successfully used in specialized applications.
How tri state device can be used to control the direction of a data bus?
tri state devices carry either 0 or 1 which represents the current state o the data bus. If the tri-state device stores 1, then the data bus carries information.If the tri-state device carries 0,then the data bus is empty.
What are the Data addressing modes of TMS320C54XX processors?
Addressing Modes for TI TMS320C54xModule by: Douglas L. Jones, Swaroop Appadwedula, Matthew Berry, Mark Haun, Dima Moussa, Daniel Sachs. E-mail the authors
Summary: The TI TMS320C54x microprocessor provides a number of ways to specify the location of data to be used in calculations. Immediate addressing, direct addressing, and indirect addressing are the three main types. Knowing the basic addressing modes of a microprocessor is important because they map directly into assembly language syntax and because the need to use a particular addressing mode often dictates which instruction one picks for a given task.
Microprocessors provide a number of ways to specify the location of data to be used in calculations. For example, one of the data values to be used in an add instruction may be encoded as part of that instruction's opcode, the raw machine language produced by the assembler as it parses your assembly language program. This is known as immediate addressing. Alternatively, perhaps the opcode will instead contain a memory address which holds the data (direct addressing). More commonly, the instruction will specify that an auxiliary register holds the memory address which in turn holds the data (indirect addressing). The processor knows which addressing mode is being used by examining special bit fields in the instruction opcode.
Knowing the basic addressing modes of your microprocessor is important because they map directly into assembly language syntax. Many annoying and sometimes hard-to-find bugs are caused by inadvertently using the wrong addressing mode in an instruction. Also, in any assembly language, the need to use a particular addressing mode often dictates which instruction one picks for a given task.
Chapter five, Data Addressing, in the CPU and Peripherals [link] reference contains extended descriptions of most of the addressing modes described below.
Accumulators: src, dstWhenever the abbreviations src or dst are used in the assembly language syntax description for an instruction, it means that only the accumulators A and B may be used for that particular operand. These are seen everywhere, but two classic examples are ld, which always loads data into an accumulator from somewhere else, and sth/stl, which always store data from an accumulator to somewhere else.Examples: ld *AR5,A ; sets A = (contents of memory location pointed to by AR5) sth B,*AR7+ ; sets (contents of memory location pointed to be AR7) = B, ; and then increments AR7 by one
Memory-mapped Registers: MMR, MMRx, MMRyMany of the TMS320C54x registers are memory-mapped, meaning that they occupy real addresses at the low end of data memory space. The most commonly used of these are the auxiliary registers AR0 through AR7. Whenever the abbreviation MMR is used in the assembly language syntax description for an instruction, it means that any memory-mapped register may be used for that particular operand. Only eight instructions use memory-mapped register addressing: ldm, mvdm, mvmd, mvmm, popm, pshm, stlm, and stm. With mvmm, since the instruction accepts two memory-mapped register operands, MMRx and MMRy, only AR0-AR7 and SP may be used.Do not use an asterisk in front of ARx variables here, since this is not indirect addressing.
Examples: mvmm AR3,AR5 ; sets AR5 = AR3 stm #5,AR2 ; sets AR2 = 5 ldm AR0,A ; sets A = AR0
Immediate Addressing: #k3, #k5, K, #k9, #lkImmediate addressing means that the numerical value of the data is itself provided within the assembly instruction. Various TMS320C54x instructions allow immediate data of 3, 5, 8, 9, or 16 bits in length, which are signified in the assembly language syntax descriptions with one of the above symbols. The 16-bit form is the most common and is signified by #lk. 16-bit immediate values always require an extra instruction word and therefore take an extra machine cycle to execute.An immediate data operand is almost always specified in assembler syntax by prepending a pound sign (#) to the data. Depending on the context, the assembler may assume that you meant immediate addressing anyway.
Examples: ld #0,A ; sets A = 0 cmpm AR1,#1 ; sets flag TC = 1 if AR1 == 1; else TC = 0
Labels make this more complicated. Recall that a label in your assembly code is nothing more than shorthand for the memory address where the labeled code or data is stored. So does an instruction like stm coef,AR2 ; sets AR2 = memory address of label coef
mean to store the contents of memory location coef in AR2, or does it mean to store the memory address coef itself in AR2? The second interpretation is correct. Because the stm instruction has only one form, expecting a #lkimmediate operand, the assembler does not care whether the label is prefixed with a pound sign or not. Still, it would have been better for us to include the pound sign in the above example for clarity.
Many instructions have several versions allowing the use of different addressing modes (see ld for a good example of this). With these instructions, including the pound sign is not optional when specifying immediate addressing. The only safe rule, then, is always to prefix the label with a pound sign if you wish to specify the memory address of the label and not the contents of that address.
If you are not sure how a particular instruction has been assembled, you can always examine the .lst file produced by the assembler, and compare the hexadecimal opcodes listed to the left of the assembly instructions with the assembly opcodes given in the assembly language manual (Chapter 4 of the Mnemonic Instruction Set [link] reference).
Direct Addressing: Smem and othersIn the modes called direct addressing by TI, the instruction opcode contains a memory offset (see the "dma" bits on page 5-8 of the CPU and Peripherals [link] reference) seven bits long, which is combined with either the DP (data pointer) or SP (stack pointer) register to obtain a complete 16-bit data-memory address. This divides the data memory into pages of 128 words each.SP is initialized for you in the core file and should not need to be modified. SP-referenced direct addressing is used by the pshd, pshm, popd, and popm instructions for stack manipulation, as well as by all subroutine calls and returns, which save program addresses on the stack.
DP-referenced direct addressing is available wherever you see the Smem abbreviation in an assembly syntax description. The advantage of DP-referenced addressing over the *(lk) form described in the next section is that DP-referenced addressing will not add an extra instruction word (and corresponding extra machine cycle). The disadvantage is that it is limited to 128 words of contiguous memory, and you have to make sure that DP points to the right 128 words. DP may be changed with the ld instruction as needed.
Examples: ld 10,A ; sets A = (contents of memory location DP + 10) add 6,B ; sets B = B + (contents of memory location DP + 6)
NOTE:Make sure you understand that the numbers 10 and 6 above are interpreted as memory addresses, not data values. To get data values, you would need to use a pound sign in front of the numbers. Absolute Addressing: dmad, pmad, *(lk)/SmemThis seems to be TI's term for all the forms of direct addressing which it does not call direct addressing! It is represented in assembly-instruction syntax-definitions using one of the above abbreviations (*(lk) addressing is available when the syntax definition says Smem). dmaddmad (Data Memory ADdress) operands are used by mvxxdata move instructions and represent 16-bit memory addresses in data memory whose contents are used in the instruction.Example: f3ptr .word 0 ; reserve one word of storage; initialize to 0 . . . . mvdm f3ptr,AR4 ; set AR4 = memory address of f3ptr
pmadpmad (Program Memory ADdress) operands are used by the firs, macd, macp, mvdp, and mvpd instructions, as well as all subroutine calls and branching instructions. They represent 16-bit addresses in program memory whose contents are used in the instruction, or jumped to in the case of branch instructions. Other than subroutine calls and branches, the most common use of a pmad is for the firs instruction.Example: firs *AR3+,*AR4+,coefs
NOTE:coefs is a label in the program section of the code, not the data section. *(lk)*(lk) addressing is a syntactic oddity. The asterisk symbol generally means that indirect addressing is being used (see below), but this is actually direct addressing with a 16-bit data memory address encoded in the instruction's last word. The reason for the asterisk is that TI does set the "I" bit in the opcode, usually denoting indirect addressing, and this form can only be used when an Smem is called for in the assembly syntax. Other bits in the low byte of the first instruction word tell the processor that the "*(lk) exception" is to be used, and to fetch the memory address in the next word (see the MOD bits on page 5-10 of the CPU and Peripherals [link] reference). You can easily recognize this addressing mode in .lst files because the low byte of the first instruction word always equals F8h.Examples: hold .word 1 ; reserve one word of storage and initialize to 1 count .word 0 ; reserve one word of storage and initialize to 0 . . . . ld *(count),B ; sets B = 0 (assuming memory was not changed) st T,*(hold) ; sets (storage location at address hold) = T
Indirect Addressing: Smem, Xmem, YmemIndirect addressing on the TMS320C54x always uses the auxiliary registers AR0 through AR7 and comes in two basic flavors. These are easily recognized from the assembly language syntax descriptions as either Smem orXmem/Ymem. SmemIn Smem indirect addressing, only one indirect address is used in the instruction and a number of variations is possible (see the table on page 5-13 of the CPU and Peripherals [link] reference). An asterisk is always used, which signifies indirect addressing. Any of the registers AR0-AR7 may be used, with optional modifications: automatic post-decrement by one, pre- and post-increment by one, post-increment and post-decrement by n (n being stored in AR0), and more, including many options for circular addressing (which automatically implements circular buffers) and bit-reversed addressing (which is useful for FFTs). Xmem/YmemXmem/Ymem indirect addressing is generally used in instructions that need two different indirect addresses, although there are a few instances where an Xmem by itself is specified in order to save bits in the opcode for other options. In Xmem/Ymem indirect addressing, fewer bits are used to encode the option modifiers in the opcode; hence, fewer options are available: post-increment by one, post-decrement by one, and post-increment by AR0with circular addressing.Examples: stl B,*AR6 ; sets (contents of location pointed to by AR6) = low word of B stl B,*AR6+0% ; sets (contents of location pointed to by AR6) = low word of B, ; then increments AR6 with circular addressing mar *+AR3(-6) ; decrements AR3 by 6 (increment by -6)
NOTE:The mar (modify address register) instruction is unusual in the sense that it takes an Smem operand but does nothing with the data pointed to by the ARx register. Its purpose is to perform any of the allowed register modifications discussed above without having to do anything else. This is often handy when you are using an Xmem/Ymem-type instruction but need to do an ARx modification that is only allowed with an Smem-type operand. SummaryThe ld instruction is illustrative of the many possible addressing modes which can be selected with the proper choice of assembly language syntax: ld #0,A ; immediate data: sets A = 0 ld 0,A ; DP-referenced direct: sets A = (contents of the address DP + 0) ld mydata,A ; DP-referenced direct: sets A = (contents of the address ; DP + lower seven bits of mydata) ld #mydata,A ; immediate data: sets A = 16 bit address mydata ld *(mydata),A ; *(lk) direct: sets A = (contents of the 16 bit address mydata) ld B,A ; accumulator: sets A = B ld *AR1+,A ; indirect: sets A = (contents of address pointed to by AR1), ; and afterwards increments AR1 by one ldm AR2,A ; memory-mapped register: sets A = AR2In paged system Can the logical address space b larger than physical address space?
Yes. This is the fundamental premise of paged or virtual memory - that you can have more logical memory than physical memory.
When does the overflow flag in 8086 set?
In the 8086/8088, the overflow flag is set when the result of an arithmetic instruction exceeds the bounds of the signed representation of a number. This is not the same as the carry flag, which is used for the unsigned representation. Both flags get set as needed. You decide which one to pay attention to.
Each data transfer is 3 clock cycles. The first cycle emits address and status, and ALE is used to strobe the low order address. Status is S0, S1, and IO/M- The second cycle sets up the transfer, either floating the data bus for a read, or drving the data bus for a write, and then initiating transfer with RD- or WR-. If READY is not true at the sample point (about the middle of the second cycle) an extra cycle is appended after the second cycle, with all lines frozen, until READY goes true. The third cycle wraps up the transfer. The processor samples data one half cycle before the end of RD- for a read, and it holds the data bus valid for one half cycle after WR- for a write. Up to this point, all cycles are similar. What matters is IO/M-. If high, this is an IO read or IO write; if low, this is a memory read or memory write. However, you have to consider S0 and S1. These are advanced status pins, along with IO/M-, that indicate what the processor is doing. They are emitted at ALE. In addition to indicating IO Read, IO Write, Memory Read, and Memory Write, you can decode Opcode Fetch, Interrupt Acknowledge, and Halt.
How does a microprocessor work?
About the same as any other stored program electronic digital computer CPU has since the Manchester Baby did when it first operated in 1948. However the microprocessor is much smaller, faster, and consumes less power per calculation than any earlier CPU.
What is the Difference between Carry and auxiliary carry?
The carry flag indicates a carry or borrow resulting from an operation. You can use it to build multi-precision representations. The auxillary carry is very much the same, except it indicates a decimal carry or borrow, useful when representing BCD digits, and can then be used in the various "adjust for addition", etc. type of instructions. (DAA, AAA, etc.)
What is program segment prefix in msdos?
The program segment prefix (PSP) in MSDOS is the first 256 bytes of memory allocated by the command interpreter to load and run a program. The program itself is loaded next. The first 128 bytes of the PSP contains various structures and pointers. The second 128 bytes of the PSP initially contain the command line, and is then available as the default disk buffer for subsequent I/O.
